Symbol Technologies Network Card CXP854P60 User Manual

CXP854P60  
CMOS 8-bit Single-chip Microcomputer  
Description  
64 pin SDIP (PIastic)  
64 pin QFP (PIastic)  
The CXP854P60 are a highly integrated micro-  
computers composed of a 8-bit CPU, PROM, RAM,  
and I/O ports. These chips feature many other high-  
performance circuits in a single-chip CMOS design,  
including an A/D converter, serial interface,  
timer/counter, time-base timer, vector interrupt, on-  
screen display function, I2C bus interface, PWM  
generator, remote control receiver, HSYNC counter,  
and watchdog timer.  
Also, the CXP854P60 provides power-on reset  
and sleep functions. The designers have ensured  
low power consumption for these powerful micro-  
computers.  
Structure  
Silicon gate CMOS IC  
Incorporating a one-time PROM, the CXP854P60  
has an equivalent function to the CXP85460 and  
character ROM for OSD can be written. Therefore, it  
is suitable for evaluation in system development  
and for the production of small amounts.  
Features  
Instruction set which supports a wide array of data types-213 types of instructions which include 16-bit  
calculations, multiplication and division arithmetic, and boolean operations.  
Minimum instruction cycle  
0.5µs/8MHz  
On-chip PROM  
60K bytes (For program)  
10K bytes (For OSD)  
On-chip RAM  
960 bytes  
On-screen display function  
12 × 18 dots, 384 types, 12lines of 32 characters  
Black frame output, half blanking, shadow, background color on full screen  
Double scanning mode supported includes jitter elimination circuit  
I2C bus interface  
14-bit PWM output, 8-bit PWM output (8 channels)  
Remote control receiver circuit  
8-bit A/D converter (4 channels, 20µs conversion time/4MHz, 8MHz)  
HSYNC counter (2channels)  
Watchdog timer  
8-bit synchronized serial I/O  
8-bit timer, 8-bit timer/counter, 19-bit time-base timer  
General purpose input/output 32-line I/O (bit-selectable input/output), also 6-line input, 10-line output (internal  
8-line Nch-O/D)  
Interrupts  
13 factors, 13 vectors, multiple interrupt possible  
SLEEP  
Standby mode  
Package  
64-pin plastic SDIP/QFP  
Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components  
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.  
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by  
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the  
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.  
– 1 –  
E95109A16-PS  
 
CXP854P60  
Pin Assignment (Top View)  
HSYNC/PA7  
VDD  
Vpp  
VSS  
MP  
1
2
64  
63  
VSYNC/PA6  
PA5  
3
62  
PA4  
4
5
61  
60  
PF0/PWM0  
PA3  
6
PF1/PWM1  
PA2  
PA1  
PA0  
PB7  
59  
58  
57  
56  
PF2/PWM2  
7
8
PF3/PWM3  
9
PF4/PWM4/SCL0  
PF5/PWM5/SCL1  
PF6/PWM6/SDA0  
10  
55  
54  
PB6  
PB5  
11  
12  
53  
52  
PB4  
PF7/PWM7/SDA1  
YM  
13  
PB3  
YS  
PB2  
14  
15  
51  
50  
I
PB1  
16  
17  
PB0  
B
49  
48  
G
PC7  
PC6  
18  
19  
47  
46  
45  
44  
R
PC5  
EXLC  
XLC  
PC4  
20  
21  
PE0/INT0  
PE1/INT1  
PE2/AN0  
PE3/AN1  
PE4/AN2  
PE5/AN3  
PE6/PWM  
PE7/TO  
PC3  
PC2  
22  
23  
43  
42  
41  
PC1  
PC0  
24  
25  
EC/PD7  
RMC/PD6  
HS1/PD5  
40  
39  
26  
27  
38  
37  
36  
28  
29  
HS0/PD4  
SI/PD3  
SO/PD2  
SCK/PD1  
VSS  
RST  
EXTAL  
XTAL  
30  
31  
35  
34  
32  
33  
PD0/INT2  
Note) 1. Vpp pin 63 must be connected to VDD.  
2. Vss pins 32 and 62 must have a common GND.  
3. MP pin 61 must be connected to GND.  
56 55 54 53  
64 63 62  
61 60 59 58 57  
52  
51  
50  
PA1  
PA0  
PB7  
PB6  
PB5  
PB4  
PB3  
PB2  
PB1  
1
PF3/PWM3  
2
PF4/PWM4/SCL0  
PF5/PWM5/SCL1  
PF6/PWM6/SDA0  
3
4
5
6
49  
48  
47  
PF7/PWM7/SDA1  
YM  
46  
45  
7
8
YS  
I
44  
43  
9
B
PB0  
PC7  
PC6  
PC5  
PC4  
PC3  
PC2  
10  
11  
42  
G
R
41  
40  
39  
12  
13  
14  
EXLC  
XLC  
38  
37  
36  
35  
34  
33  
PE0/INT0  
PE1/INT1  
PE2/AN0  
PE3/AN1  
PE4/AN2  
PE5/AN3  
15  
16  
PC1  
PC0  
17  
18  
19  
EC/PD7  
21 22  
25  
31 32  
29  
20  
23 24  
26 27 28  
30  
Note) 1. Vpp pin 56 must be connected to VDD.  
2. Vss pins 26 and 58 must have a common GND.  
3. MP pin 55 must be connected to GND.  
3 –  
 
CXP854P60  
Pin Functions  
Pin Name  
I/O  
Function  
(Port A)  
Single bit selectable 8-bit port.  
(8 lines)  
PA0 to PA5  
I/O  
PA6/VSYNC  
PA7/HSYNC  
I/O/Input  
I/O/Input  
CRT display vertical synchronization signal input pin.  
CRT display horizontal synchronization signal input pin.  
(Port B)  
PB0 to PB7  
I/O  
Single bit selectable 8-bit port.  
(8 lines)  
(Port C)  
PC0 to PC7  
PD0/INT2  
I/O  
Single bit selectable 8-bit port.  
(8 lines)  
Input pin for external interrupt request.  
Active on falling edge.  
I/O/Input  
PD1/SCK  
PD2/SO  
PD3/SI  
I/O/I/O  
Serial clock pin.  
(Port D)  
I/O/Output  
I/O/Input  
I/O/Input  
I/O/Input  
I/O/Input  
I/O/Input  
Single bit selectable Serial data output pin.  
8-bit port.  
Serial data input pin.  
12mA sink current  
PD4/HS0  
PD5/HS1  
PD6/RMC  
PD7/EC  
drive possible.  
(8 lines)  
HSYNC counter (CH0) input pin.  
HSYNC counter (CH1) input pin.  
Remote control receiver circuit input pin.  
External event timer/counter input pin.  
Input pin for external interrupt request.  
Active falling edge.  
(2 lines)  
PE0/INT0  
PE1/INT1  
Input/Input  
Input/Input  
(Port E)  
PE2/AN0  
to  
PE5/AN3  
8-bit port, lower  
6 bits for input,  
upper 2 bits for  
output.  
Analog input pin for A/D converter.  
(4 lines)  
14-bit PWM output pin.  
(CMOS output)  
PE6/PWM  
PE7/TO  
Output/Output  
Output/Output  
(8 lines)  
Square wave output for timer 1.  
(50% duty cycle)  
PF0/PWM0  
to  
PF3/PWM3  
8-bit PWM output pin.  
(8-lines)  
Output/Output  
(Port F)  
8-bit output port  
with large current  
(12mA) N-ch open  
drain output.  
Lower 4 bits middle  
voltage tolerance  
(12V), upper 4 bits  
PF4/PWM4/  
SCL0  
PF5/PWM5/  
SCL1  
Output/Output/  
I/O  
I2C bus interface transfer clock I/O pin.  
I2C bus interface transfer data I/O pin.  
PF6/PWM6/  
SDA0  
PF7/PWM7/  
SDA1  
Output/Output/ 5V suppression.  
I/O (8 lines)  
R, G, B, I, YS, YM Output  
CRT display 6-bit output pin.  
4 –  
 
CXP854P60  
Pin Name  
EXLC  
I/O  
Function  
CRT display clock oscillator I/O pin.  
Input  
Oscillator frequency is determined external L, C circuit.  
XLC  
Output  
Input  
EXTAL  
XTAL  
System clock oscillator crystal connection pin. When using an external  
clock, input to EXTAL pin and leave XTAL pin open.  
Output  
"L" level active system reset. This pin also acts as an I/O pin during  
power up. While internal power-on reset function is talking place a  
"L" level is output.  
RST  
I/O  
MP  
Input  
Test mode input pin. Must be connected to GND.  
Positive power supply pin for incorporated PROM writing.  
Under normal operating conditions, connect to VDD.  
Vpp  
VDD  
Positive supply voltage pin.  
Vss  
GND. Both Vss pins should be connected to common GND.  
5 –  
 
CXP854P60  
When reset  
Pin Equivalent I/O Circuit  
Pin  
Circuit format  
Port A  
Port B  
Port C  
Port A data  
Port B data  
Port C data  
PA0 to PA5  
PB0 to PB7  
PC0 to PC7  
Port A direction  
Port B direction  
Port C direction  
Hi-Z  
Input protection  
circuit  
IP  
Data bus  
RD  
(Port A, B, C)  
22 lines  
Port A  
Port A data  
Port A direction  
PA6/VSYNC  
PA7/HSYNC  
Input protection  
circuit  
IP  
Data bus  
Hi-Z  
RD (Port A)  
VSYNC  
HSYNC  
Schmitt input  
Input multiplexer  
2 lines  
Port D  
PD0/INT2  
PD3/SI  
PD4/HS0  
PD5/HS1  
Port D data  
Port D direction  
Large current  
source 12mA  
Hi-Z  
PD6/RMC  
PD7/EC  
IP  
Data bus  
RD (Port D)  
INT2, SI, HS0, HS1, RMC, EC  
Schmitt input  
6 lines  
6 –  
 
CXP854P60  
When reset  
Pin  
Circuit format  
Port D  
SCK or SO  
Output enable  
Large current  
source 12mA  
PD1/SCK  
PD2/SO  
Port D data  
Port D direction  
Hi-Z  
IP  
Schmitt input  
Data bus  
RD (Port D)  
SCK only  
2 lines  
Port E  
Schmitt input  
IP  
PE0/INT0  
PE1/INT1  
(To interrupt circuit)  
Data bus  
Hi-Z  
2 lines  
RD (Port E)  
Port E  
Input multiplexer  
PE2/AN0  
to  
PE5/AN3  
IP  
To A/D converter  
Hi-Z  
Data bus  
RD (Port E)  
4 lines  
Port E  
TO, PWM  
PE6/PWM  
PE7/TO  
H level  
Port E data  
Port E selection  
2 lines  
7 –  
 
CXP854P60  
When reset  
Pin  
Circuit format  
Port F  
PWM  
PF0/PWM0  
to  
12V voltage torelance  
PF3/PWM3  
Port F data  
Port F selection  
Hi-Z  
Large current  
source 12mA  
4 lines  
Port F  
SCL, SDA  
PF4/PWM4/  
SCL0  
PF5/PWM5/  
SCL1  
Large current  
source 12mA  
I2C output enable  
PWM  
PF6/PWM6/  
SDA0  
PF7/PWM7/  
SDA1  
Hi-Z  
Port F data  
IP  
Port F selection  
BUS SW  
Schmitt input  
SCL, SDA  
(To I2C circuit)  
To other I2C pins  
4 lines  
R
G
B
R, G, B, I, YS, YM  
Output polarity  
I
Hi-Z  
YS  
YM  
To output polarity register  
Writing data to port register brings output  
from high impedance to active  
6 lines  
IP  
Oscillator control  
EXLC  
XLC  
EXLC  
XLC  
Oscillation  
halted  
CRT display clock  
IP  
2 lines  
8 –  
 
CXP854P60  
When reset  
Pin  
Circuit format  
Diagram indicates equivalent  
circuit during oscillation  
EXTAL  
XTAL  
EXTAL  
XTAL  
IP  
Feedback resistor is disconnected  
during STOP  
Oscillation  
2 lines  
Pull-up resistor  
Schmitt input  
RST  
L level  
From power-on reset circuit  
1 line  
9 –  
 
CXP854P60  
Absolute Maximum Ratings  
(Vss = 0V)  
Item  
Symbol  
VDD  
Ratings  
Unit  
V
Remarks  
0.3 to +7.0  
0.3 to +13.0  
Supply voltage  
Vpp  
VIN  
V
Incorporated PROM  
Pins PF0 to PF3  
1  
Input voltage  
0.3 to +7.0  
V
1  
Output voltage  
VOUT  
VOUTP  
IOH  
0.3 to +7.0  
V
Medium voltage tolerance output voltage  
High level output current  
High level total output current  
0.3 to +15.0  
V
5  
50  
mA  
mA  
mA  
mA  
mA  
°C  
°C  
IOH  
IOL  
Total of all output pins  
15  
Excludes large current output  
Low level output current  
2  
IOLC  
20  
Large current output  
IOL  
Topr  
Tstg  
130  
Total of all output pins  
Low level total output current  
Operating temperature  
Storage temperature  
10 to +75  
55 to +150  
1000  
mW SDIP  
mW QFP  
Allowable power dissipation  
PD  
600  
1  
VIN and VOUT should not exceed VDD + 0.3V.  
2  
The large current driver for the PD and PF ports is a N-ch transistor.  
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should  
better take place under the recommended operating conditions. Exceeding those conditions may  
adversely affect the reliability of the LSI.  
Recommended Operating Conditions  
(Vss =0V)  
Item  
Symbol  
Min.  
4.5  
3.5  
2.5  
Max.  
5.5  
Unit  
V
Remarks  
Safe operating range  
1  
VDD  
5.5  
Safe operating range for low speed data  
V
Supply voltage  
5.5  
Safe operating range for data retention during STOP  
V
5  
Vpp = VDD  
V
Vpp  
VIH  
2  
0.7VDD  
0.8VDD  
VDD  
VDD  
I2C Schmitt input included  
V
High level  
input voltage  
3  
CMOS Schmitt input  
V
VIHS  
VIHEX  
VIL  
4  
EXTAL pin  
I2C Schmitt input included  
VDD 0.4 VDD + 0.3  
V
2  
0
0
0.3VDD  
0.2VDD  
0.4  
V
Low level  
input voltage  
3  
CMOS Schmitt input  
V
VILS  
VILEX  
Topr  
4  
EXTAL pin  
0.3  
10  
V
Operating temperature  
+75  
°C  
1  
Rating for 1/16 frequency mode and sleep mode.  
2  
3  
Normal input port (All pins PA, PB, PC, PE2 to PE5), PF4 to PF7 pins.  
Includes PD0/INT2, PD1/SCK, PD2, PD3/SI, PD4/HS0, PD5/HS1, PD6/RMC, PD7/EC, PE0/INT0, PE1/INT1,  
HSYNC, VSYNC, RST pins.  
4  
5  
Rating applies to external clock input only.  
Vpp and VDD should be set to a same voltage.  
10 –  
 
CXP854P60  
DC Characteristics  
(Ta = 10 to +75°C, Vss = 0V)  
Symbol  
VOH  
Item  
Pin  
Condition  
Min. Typ. Max. Unit  
VDD = 4.5V, IOH = 0.5mA  
VDD = 4.5V, IOH = 1.2mA  
V
V
V
4.0  
3.5  
High level  
output voltage  
PA to PD, PE6, PE7,  
R, G, B, I, YS, YM  
PA to PD, PE6, PE7,  
R, G, B, I, YS, YM,  
PF0 to PF3, RST  
VDD = 4.5V, IOL = 1.8mA  
0.4  
VDD = 4.5V, IOL = 3.6mA  
VDD = 4.5V, IOL = 12.0mA  
VDD = 4.5V, IOL = 3.0mA  
0.6  
1.5  
0.4  
V
V
V
Low level  
output voltage  
PD, PF  
VOL  
PF4 to PF7  
(SCL0, SCL1,  
SDA0, SDA1)  
VDD = 4.5V, IOL = 4.0mA  
0.6  
40  
V
IIHE  
IIHL  
IILR  
VDD = 5.5V, VIH = 5.5V  
VDD = 5.5V, VIL = 0.4V  
VDD = 5.5V, VIL = 0.4V  
0.5  
µA  
µA  
EXTAL  
Input current  
0.5  
1.5  
40  
RST  
400 µA  
PA to PE, HSYNC,  
VSYNC, R, G, B, I,  
YS, YM  
VDD = 5.5V,  
VI = 0, 5.5V  
I/O leakage current  
IIZ  
±10  
µA  
Open drain output  
leak current  
(N-ch Tr off case)  
PF0 to PF3  
PF4 to PF7  
VDD = 5.5V, VOH = 12.0V  
VDD = 5.5V, VOH = 5.5V  
50  
10  
µA  
µA  
ILOH  
RBS  
I2C bus switch  
connection impedance  
(Output Tr off case)  
VDD = 4.5V  
VSCL0 = VSCL1 = 2.25V  
VSDA0 = VSDA1 = 2.25V  
SCL0: SCL1  
SDA0: SDA1  
120  
Operating mode  
(1/2, clock rate)  
20  
IDD  
8MHz crystal oscillator  
(C1 = C2 = 22pF)  
All output pins open  
mA  
35  
VDD1  
Supply current  
SLEEP mode  
mA  
µA  
IDDSL  
IDDST  
1.0  
3
2  
STOP mode  
1MHz clock  
0V for non-measurement pins  
Pins other than  
VDD and Vss  
10  
20  
pF  
Input capacitance  
CIN  
1  
2  
Rating applies only if OSD oscillator is halted.  
This device does not enter in the stop mode.  
11 –  
 
CXP854P60  
AC Characteristics  
(1) Clock timing  
(Ta = 10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)  
Item  
System  
Pin  
Condition  
Fig. 1, Fig. 2  
Min.  
3.5  
Max.  
9
Unit  
XTAL  
EXTAL  
System clock frequency  
fC  
MHz  
t
XL,  
tXH  
Fig. 1, Fig. 2  
External clock drive  
System clock input  
pulse width  
ns  
EXTAL  
50  
System clock  
rise and fall times  
t
CR,  
tCF  
Fig 1, Fig 2  
External clock drive  
ns  
ns  
EXTAL  
EC  
200  
20  
Event counter input  
clock pulse widtth  
t
tEL  
EH,  
Fig. 3  
Fig. 3  
tsys + 50  
Event counter input clock  
rise and fall times  
t
tEF  
ER,  
ms  
EC  
tsys indicates one of three values according to the contents of the clock control register. (For CPU clock  
selection.)  
tsys (ns) = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")  
Fig. 1. Clock timing  
1/fc  
VDD 0.4V  
EXTAL  
0.4V  
tXH  
tCF  
tXL  
tCR  
Fig. 2. Clock applied condition  
Crystal oscillator  
Ceramic oscillator  
External clock  
EXTAL  
XTAL  
EXTAL  
XTAL  
C1  
C2  
OPEN  
Fig. 3. Event count clock timing  
0.8VDD  
0.2VDD  
EC  
tEH  
tEF  
tEL  
tER  
12 –  
 
CXP854P60  
(2) Serial transfer  
Item  
(Ta = 10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)  
System  
Pin  
Condition  
Input mode  
Min.  
1000  
Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SCK cycle time  
SCK  
tKCY  
Output mode  
8000/fc  
400  
SCK input mode  
SCK output mode  
SCK input mode  
SCK output mode  
SCK input mode  
SCK output mode  
SCK input mode  
SCK output mode  
SCK  
tKH  
tKL  
SCK  
SI  
high and low level widths  
4000/fc 50  
100  
SI input set-up time  
(referenced to SCK )  
tSIK  
tKSI  
tKSO  
200  
200  
SI input hold time  
(referenced to SCK )  
SI  
100  
200  
100  
SCK ↓ → SO delay time  
SO  
Note) For SCK output mode, in addition to output delay time SO capacitance must be 50pF + 1TTL.  
Fig. 4. Serial transfer timing  
tKCY  
tKL  
tKH  
0.8VDD  
0.2VDD  
SCK  
tSIK  
tKSI  
0.8VDD  
0.2VDD  
Input data  
SI  
tKSO  
0.8VDD  
SO  
Output data  
0.2VDD  
13 –  
 
CXP854P60  
(3) Interrupt, Reset input  
Item  
(Ta = 10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)  
Symbol  
Pin  
Condition Min.  
Max.  
Unit  
µs  
External interrupt  
high and low level widths  
tIH  
tIL  
INT0 to  
INT2  
1
Reset input low level width  
8/fc  
µs  
tRSL  
RST  
Fig. 5. Interrupt input timing  
tIH  
tIL  
0.8VDD  
INT0 to INT2  
(falling edge)  
0.2VDD  
Fig. 6. RST input timing  
tRSL  
RST  
0.2VDD  
(4) Power-on reset  
Power on reset  
(Ta = 10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)  
Item  
Symbol Pin  
Condition  
Min.  
0.05  
1
Max. Unit  
Power supply rise time  
tR  
50  
ms  
ms  
Power-on reset  
VDD  
Power supply cutt-off time tOFF  
Repeated power-on reset  
Fig. 7. Power-on reset  
4.5V  
0.2V  
VDD  
0.2V  
tR  
tOFF  
Take care when turning on power.  
14 –  
 
CXP854P60  
(5) A/D converter characteristics  
(Ta = 10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)  
Item  
Resolution  
Symbol  
Pin  
Condition  
Min.  
Typ.  
Max.  
8
Unit  
Bits  
LSB  
Linearity error  
±1  
Zero transition  
voltage  
Ta = 25°C  
VDD = 5.0V  
Vss = 0V  
VZT1  
10  
10  
70  
mV  
mV  
Full-scale transition  
voltage  
VFT2  
4910  
4970  
5030  
160/fADC3  
Conversion time  
Sampling time  
tCONV  
tSAMP  
µs  
µs  
V
12/fADC3  
AN0 to AN3  
Analog input voltage VIAN  
0
VDD  
Fig. 8. Definitions for A/D converter terms  
FFH  
FEH  
1  
2  
3  
VZT: Digital conversion values change between 00H01H.  
VFT: Digital conversion values change between 0EH0FH.  
fADC indicates the below values due to the bit6 (CKS) of A/D  
control registor (address: 00F6H) and the Bit 7 (PCK1) and  
Bit 6 (PCK0) of clock control registor (address: 00FEH)  
Linearity error  
CKS  
01H  
00H  
0 (φ/2 selection) 1 (φ/2 selection)  
PCK1, 0  
VZT  
VFT  
00 (φ = fEX/2)  
01 (φ = fEX/4)  
11 (φ = fEX/16)  
fADC = fC/2  
fADC = fC/4  
fADC = fC/16  
fADC = fC  
fADC = fC/2  
fADC = fC/8  
Analog input  
15 –  
 
CXP854P60  
(6) I2C bus timing  
(Ta = 10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)  
Item  
Symbol  
fSLC  
Pin  
SCL  
Condition  
Min.  
0
Max.  
100  
Unit  
kHz  
µs  
SCL clock frequency  
Bus free time before starting transfer  
Hold time for starting transfer  
Clock low level width  
tBUF  
SDA, SCL  
SDA, SCL  
SCL  
4.7  
4.0  
4.7  
4.0  
4.7  
tHD; STA  
tLOW  
µs  
µs  
Clock high level width  
tHIGH  
SCL  
µs  
Set-up time for repeated transfers  
Data hold time  
tSU; STA  
tHD; DAT  
tSU; DAT  
SDA, SCL  
SDA, SCL  
SDA, SCL  
SDA, SCL  
SDA, SCL  
SDA, SCL  
µs  
0
µs  
Data set-up time  
0.25  
µs  
SDA, SCL rise time  
tR  
1
µs  
SDA, SCL fall time  
tF  
0.3  
µs  
Set-up time for transfer completion  
tSU; STO  
4.7  
µs  
Since SCL rise time (max: 300ns) is not considered part of data hold time, allow at least 300ns.  
Fig. 9. I2C bus transfer data timing  
SDA  
tBUF  
tR  
tF  
tHD; STA  
SCL  
tHD; STA  
tSU; STO  
tSU; STA  
P
S
St  
P
tLOW  
tHD; DAT  
tHIGH  
tSU; DAT  
Fig. 10. I2C device suggested circuit  
I2C  
device  
I2C  
device  
RS  
RS RS  
RS RP  
RP  
SDA0  
(or SDA1)  
SCL0  
(or SCL1)  
A pull-up resistor must be connected to SDA0 (or SDA1), and SCL0 (or SCL1).  
The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300or less) can be used to reduce spike  
noise caused by CRT flashover.  
16 –  
 
CXP854P60  
(7) OSD (On Screen Display) timing  
(Ta = 10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)  
Shadow Existent  
Shadow Non-existent  
Item  
Symbol  
Pin  
Condiiton  
Fig. 12  
Unit  
Min.  
Max.  
Min.  
Max.  
1  
1  
7
11  
EXLC  
XLC  
OSD clock frequency  
HSYNC pulse width  
fOSC  
4
4
MHz  
2  
2  
14  
16  
tHWD  
tHCG  
HSYNC Fig. 11  
HSYNC Fig. 11  
1.2  
1.2  
µs  
ns  
HSYNC afterwrite  
rise and fall times  
200  
1.0  
200  
1.0  
VSYNC afterwrite  
rise and fall times  
µs  
tVCG  
VSYNC Fig. 11  
1  
2  
Oscillator clock at 4MHz operation  
Oscillator clock at 8MHz operation  
Fig. 11. OSD timing  
tHCG  
tHWD  
0.8VDD  
HSYNC  
For OPOL register (01FAH)  
bit 7 at 0”  
0.2VDD  
tVCG  
0.8VDD  
0.2VDD  
VSYNC  
For OPOL register (01FAH)  
bit 6 at 0”  
Fig. 12. LC oscillator circuit connection  
EXLC  
XLC  
L
C2  
C1  
17 –  
 
CXP854P60  
Supplement  
Fig. 13. SPC700 Series recommended oscillation circuit  
(i)  
(ii)  
EXTAL  
XTAL  
Rd  
EXTAL  
XTAL  
Rd  
C1  
C2  
C1 C2  
Circuit  
Example  
Manufacturer  
Model  
fc (MHz)  
C1 (pF)  
C2 (pF)  
Rd ()  
CSA4.00MG  
CSA4.19MG  
CSA8.00MTZ  
CST4.00MGW  
CST4.19MGW  
4.00  
4.19  
8.00  
4.00  
4.19  
8.00  
4.00  
4.19  
8.00  
4.00  
4.19  
8.00  
(i)  
MURATA MFG  
CO., LTD.  
30  
30  
0
(ii)  
(i)  
(i)  
CST8.00MTW  
RIVER ELETEC  
CO., LTD.  
12  
27  
0
0
12  
27  
HC-49/U03  
HC-49/U(-S)  
KINSEKI LTD.  
Indicates types with on-chip grounding capacitors (C1 and C2).  
Product List  
Option item  
CXP854P60S-1-  
CXP854P60Q-1-  
Mask product  
64-pin plastic  
SDIP/QFP  
64-pin plastic  
SDIP/QFP  
Package  
Program ROM capacitance  
Reset pin pull-up resistor  
Power-on reset circuit  
Font data  
52K/60K byte  
Existent/Non-existent  
Existent/Non-existent  
User specified  
PROM 60K byte  
Existent  
Existent  
User specified (PROM)  
The font data for the one-time PROM version is operated in the same way as the program writing.  
18 –  
 
CXP854P60  
Fig. 14. Characteristics curves  
IDD vs. VDD  
(fc = 8MHz, Ta = 25°C, Typical)  
IDD vs. fc  
(VDD = 5V, Ta = 25°C, Typical)  
20  
18  
16  
1/2 frequency mode  
1/4 frequency mode  
10  
1/2 frequency mode  
1/16 frequency mode  
SLEEP mode  
14  
12  
10  
8
1
1/4 frequency mode  
6
0.1  
2
3
4
5
6
4
1/16 frequency mode  
SLEEP mode  
VDD Supply voltage [V]  
2
0
1
5
10  
fc System clock [MHz]  
Parameter Curve for OSD Oscillator L vs. C  
(Analytically calculated value)  
100  
5.0MHz  
6.5MHz  
10  
13.0MHz  
1
fOSC =  
C = C1 // C2  
2π√ LC  
0
50  
100  
C1, C2 Capacitance [pF]  
19 –  
 
CXP854P60  
Package Outline  
Unit: mm  
64PIN SDIP (PLASTIC)  
+ 0.4  
57.6 – 0.1  
33  
64  
0˚ to 15˚  
1
32  
1.778  
0.5 ± 0.1  
0.9 ± 0.15  
PACKAGE STRUCTURE  
PACKAGE MATERIAL  
LEAD TREATMENT  
LEAD MATERIAL  
PACKAGE MASS  
EPOXY RESIN  
SONY CODE  
EIAJ CODE  
SOLDER PLATING  
SDIP-64P-01  
P-SDIP64-17.1x57.6-1.778  
42/COPPER ALLOY  
8.6g  
JEDEC CODE  
64PIN SDIP (PLASTIC)  
+ 0.4  
57.6 0.1  
33  
64  
0˚ to 15˚  
1
32  
1.778  
0.5 ± 0.1  
0.9 ± 0.15  
PACKAGE STRUCTURE  
PACKAGE MATERIAL  
LEAD TREATMENT  
LEAD MATERIAL  
PACKAGE MASS  
EPOXY RESIN  
SONY CODE  
EIAJ CODE  
SOLDER PLATING  
SDIP-64P-01  
P-SDIP64-17.1x57.6-1.778  
42/COPPER ALLOY  
8.6g  
JEDEC CODE  
LEAD SPECIFICATIONS  
ITEM  
LEAD MATERIAL  
LEAD TREATMENT  
SPEC.  
ALLOY 42  
Sn-Bi 2.5%  
LEAD TREATMENT THICKNESS 5-18µm  
20 –  
 
CXP854P60  
Package Outline  
Unit: mm  
64PIN QFP (PLASTIC)  
23.9 ± 0.4  
+ 0.4  
20.0 0.1  
+ 0.1  
0.15 0.05  
0.15  
51  
33  
52  
32  
64  
20  
+ 0.2  
0.1 0.05  
1
19  
+ 0.35  
2.75 0.15  
+ 0.15  
0.4 0.1  
1.0  
0˚ to10˚  
M
0.2  
PACKAGE STRUCTURE  
PACKAGE MATERIAL  
LEAD TREATMENT  
LEAD MATERIAL  
EPOXY RESIN  
SOLDER PLATING  
SONY CODE  
EIAJ CODE  
JEDEC CODE  
QFP-64P-L01  
42/COPPER ALLOY  
1.5g  
P-QFP64-14x20-1.0  
PACKAGE MASS  
64PIN QFP (PLASTIC)  
23.9 ± 0.4  
+ 0.4  
20.0 0.1  
+ 0.1  
0.15 0.05  
0.15  
51  
33  
52  
32  
64  
20  
+ 0.2  
0.1 0.05  
1
19  
+ 0.35  
2.75 0.15  
+ 0.15  
0.4 0.1  
1.0  
0˚ to10˚  
M
0.2  
PACKAGE STRUCTURE  
PACKAGE MATERIAL  
LEAD TREATMENT  
LEAD MATERIAL  
EPOXY RESIN  
SOLDER PLATING  
SONY CODE  
EIAJ CODE  
JEDEC CODE  
QFP-64P-L01  
42/COPPER ALLOY  
1.5g  
P-QFP64-14x20-1.0  
PACKAGE MASS  
LEAD SPECIFICATIONS  
ITEM  
LEAD MATERIAL  
LEAD TREATMENT  
SPEC.  
ALLOY 42  
Sn-Bi 2.5%  
LEAD TREATMENT THICKNESS 5-18µm  
Sony Corporation  
21 –  
 

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